1. Field of the Invention
The present invention relates to a lead frame for use in a semiconductor device of resin-sealed type, and relates in particular to a pre-plated frame (which will hereinafter be abbreviated as a PPF) in which the outer lead portion is solder-plated in advance.
2. Description of the Prior Art
FIG. 1A shows a current predominant assembling process of a semiconductor device of resin-sealed type. In accordance with the process, a wafer is diced into chips. Then, the obtained chip is die-bonded with silver paste onto a lead frame in which a die pad portion and an inner lead portion are silver-plated. Subsequently, wire-bonding between the inner lead portion and the chip is conducted using gold wires. Thereafter, the thus formed structure is sealed with a molding resin. After the molding resin-sealing step, the outer lead portion is subjected to surface treatments such as solder plating, tin plating, solder dipping and the like. Then, the operation is followed successively by forming, marking electric examination and an appearance observation check.
Meanwhile, in order to reduce the processing time taken after the molding step, an assembling process has been proposed in which use is made of a preplated frame (PPF) or a lead frame having not only an inner lead portion and a die pad portion silver-plated but also having an outer lead portion previously plated with solder or the like in the lead frame step. Such a process is disclosed, for example in Japanese Patent Application Laid-Open Sho 51 No. 115775.
FIG. 1B is a flowchart showing the assembling process using a PPF.
In the assembling process using a PPF, it is not necessary to effect solder plating and the like for outer package plating after the molding step because the PPF is formed of a lead frame in which the inner lead portion is silver-plated and the outer lead portion is solder-plated in advance.
Nevertheless, since the PPF has been provided with solder plating, if the solder layer in the outer lead portion is melted down in the assembling process, the solderability will be degraded when the semiconductor device is mounted on a board while the solder layer of the outer lead portion changes in color to thereby give bad appearance to the semiconductor device. Accordingly, it is necessary to configure a low temperature assembling process (183.degree. C. or less) in which the solder plating layer of the outer lead cannot melt and therefore cannot change in color through a series of steps.
Therefore, die bonding material and molding resin material which cure at a temperature lower than 183.degree. C. must be developed for use in the die bonding and molding steps, respectively.
In spite of such disadvantages, the use of the PPF will omit the need for effecting outer lead plating after molding, so that the processing time can be reduced by two days. Additionally, the omission of the outer plating may lead to cost reduction. For these reasons, the assembling process using the PPF has drawn attention in recent years.
FIG. 2 is a plan view showing an example of such a PPF. In the figure, the PPF is composed of outer leads 70, a solder plating layer 71 on the outer leads, inner leads 80, silver plating layer 81 on the inner leads, a die pad 90 and a silver plating layer 91 on the die pad.
Plating of outer leads used in the assembly process using such a PPF is conducted mainly by solder plating.
FIG. 3 shows a structure of plating on the outer lead. In the figure, formed on a lead frame base 11 is a solder plating layer 20, which contains tin 21 and lead 22.
For plating outer leads, tin plating can be carried out in place of solder plating, but solder plating may provide improved solderability at the time the final semiconductor device is mounted to assure the superiority of the solder plating. There are two kinds of solder to be used for solder plating in which tin and lead are compounded in ratios of 6:4 and 9:1, and the latter is used more frequently.
Moreover, there are various kinds of solder, but the solder used for plating outer leads in semiconductor devices is composed of tin and lead with no other metal compounded.
Generally, the solder plating is performed immediately on the base of a lead frame, but in some cases strike-plating may be executed using such as copper, tin/nickel and the like in order to enhance adhesion between the solder plating and the substrate or undercoating to be solder-plated.
Since solder plating is of a wet process, the frame may be heated by blowing hot air (about 100.degree. C. for ten seconds) so as to be dried after the rinsing step, but the lead frame undergoes no other heat treatment except for the drying purpose.
FIG. 4 is a sectional view showing a semiconductor device of resin-sealed type using a prior art PPF. In the figure, the structure includes a semiconductor chip 111, a die pad 90, inner lead portion 80, outer lead portion 70 and metal wires 110 for wire-bonding. In a typical prior art PPF plating structure in which 42-alloy is used as a material constituting the lead frame, a silver plating layer 81 in a wire bonding region and a solder plating layer 71 in an outer lead portion 70 do not overlap with one another while part of the solder plating layer 71 is embedded in a molding resin 116 in most cases as shown in FIG. 4. In general, the solder layer 71 may be plated directly on the 42-alloy constituting the lead frame. Alternatively, a Cu strike layer of about 0.1 to 0.3 .mu.m thick can be deposited as a substrate or undercoat as disclosed in Japanese Patent Application Laid-Open Sho 60 No. 79760. The purpose of providing the strike layer is to eliminate adverse influence of the solder-substituted plating layer adhered onto the surface of the silver plating layer. More specifically, in the process for preparing PPF, first silver plating layers 81, 91 are formed while portions other than inner lead portion 80 and die pad portion 90 being masked. Then, solder plating layer 71 will be formed while other portions than the outer lead portion 70 being masked. In this step, solder adheres onto the surface of silver plating layer to form solder-substituted plating producing a bad effect. In order to prevent the bad effect, a copper layer of about 0.3 .mu.m in thickness is coated entirely on the surface as a temporary deposition for peeling after the silver plating, thereafter solder plating will be made. In this case, as the copper plating is peeled off after completion of the solder plating, the substituted plating may be removed and no copper plating exists on the undercoating of the silver plating layer.
By the way, in use of the PPF described above, deformation of solder plating may occur between outer leads in some cases after molding.
This deformation of solder plating arises due to the deposited solder on the outer leads of the PPF. Accordingly, no deformation occurs in the aforementioned assembling process as shown in FIG. 1A in which no PPF is used.
The solder plating deformation will hereinafter be described with reference to FIGS. 5 through FIG. 8.
Initially, FIG. 5 is a plan view showing the PPF shown in FIGS. 2 and 3, clamped by mold press. In FIG. 5, lines 1 and 2 indicate clamping boundaries of a mold. Reference numeral 100 designates deformation of solder plating layer depressed between outer leads and mold-clamping portion is designated at 121.
FIG. 6 is a side-sectional view taken on a line 5-6 shown in FIG. 5, showing solder layer deformation 100 between outer leads.
Next, FIG. 7 is a side-sectional view taken on a line 3-4 shown in FIG. 5, showing a lead frame 11 clamped by a mold 120 with no molding resin filled. Here, in FIG. 7, a semiconductor chip is designated at 111 and gold wires for wire-bonding are designated at 110. A silver paste for die-bonding is denoted by 92.
FIG. 8 is a perspective view showing a semiconductor device after the forming step. Reference numeral 116 designates molding resin.
When a solder plating layer 20 on outer leads 70 is clamped as shown in FIG. 7 by a mold 120 in the molding step, portions of the solder layer under mold-clamping portion 121 are pressed and crushed to be depressed between outer leads forming burr-like deformation 100 (refer to FIGS. 5 and 6).
More specifically, in the molding step, the solder plated portion (dam bar portion and the like) is clamped with a pressure of 1 to 3 ton/cm.sup.2. This force deforms the solder layer in clamping portion 121 and presses out the layer to form deformation 100 between the leads as shown in FIGS. 5 and 6. In this state, molding resin 116 is injected into the mold cavity. After the resin curing process, lead wires are cut to be bent. To achieve this, the resin portion filled inside the dam bar is cut out. Then, as the dam bar is cut, the solder deformation 100 which has been crushed out, adheres to the side of the leads. The adhered portions will be left as flushes 101 at the lead bending step.
The deformation 100 of solder plating layer occurs frequently when Fe-alloy material such as 42-alloy (Fe: Ni=58:42) is used as a material for lead frame 11. This suggests that a solder deposited on a copper frame has a higher hardness in warm-temperature range than the same solder deposited on a Fe-alloy material.
Pronounced deformations of the solder layer may not be removed even when removal of resin burrs in tie rod portion is executed in the forming step. In such cases, flushes 101 of solder remain between outer leads 70, and this could cause short-circuits or leakage between terminals after the semiconductor device is mounted (refer to FIG. 8).
This problem is critical particularly when reliable quality is to be established in quad-flat package (QFP) type semiconductor devices having a large number of pins with a narrow outer lead pitch (0.65 mm or less).
The deformation of solder plating cannot be attributed to the solder layer being molten since the mold is used at lower temperatures than the melting point of the solder (183.degree. C. or less) but the deformation can be attributed to the great clamping pressure acted on the mold and the reduced hardness of the solder plating layer in warm-temperature range.
The mold in the molding step is used at temperatures ranging from 160.degree. to 180.degree. C. In this temperature range, hardness of the solder plating layer is low as compared to that at normal temperature. According to the experiment performed by the inventors of the present application, it was found that the solder plating layer at normal temperature has a hardness of about 16 Hk (Knoop hardness, weight: 1 g) whereas the hardness of the same solder layer at 170.degree. C. is reduced to about 5 Hk.
As the temperature of the mold during molding is lowered in order not to reduce the hardness of the solder plating layer, transfer mold becomes difficult to be performed. This means that it is impossible to decrease the temperature of the mold.
It was also confirmed by the present inventors hereof that when clamping pressure on the mold was lowered, the deformed state of the solder layer was decreased.
Actually, when clamping pressure on mold was lowered from about 2t/cm.sup.2 to about 1t/cm.sup.2, the degree of the deformation of the solder layer was improved but this measure could not lower the frequency of the deformation of solder layer.
On the other hand, when the clamping pressure on mold was reduced, resin leak occurred from the clearance between the mold and the lead frame resulting in failure to achieve resin-molding. Accordingly, it is impossible to prevent deformation of the solder layer by lowering the clamping force on mold.
It was also found that deformation of a solder layer could not occur when the solder layer was 4 .mu.m or less in thickness, and that the thicker the solder layer, the greater the solder layer was deformed.
With a layer thickness of about 7 .mu.m the solder layer was displaced to gaps between the outer leads in excess of 0.4 mm.
When a QFP having an outer lead pitch of 0.8 mm was used, the deformed solder filled up gaps between the outer leads.
When the solder layer of 7 .mu.m thick was clamped, the thickness of the layer reduced to about 4 .mu.m and the solder corresponding to the loss of thickness was crushed out between outer leads.
Accordingly, if the thickness of the solder plating layer was controlled to be 4 .mu.m or less, the problem would be eliminated. Since the controlling tolerance of the thickness of the solder layer upon production of PPF is .+-.1 .mu.m, the average thickness of the solder layer must be 3 .mu.m in order to regulate the thickness of the solder layer within 4 .mu.m or less.
Specifically, for making the solder layer of 4 .mu.m thick or less, the thickness of the solder layer will disperse between 2 .mu.m and 4 .mu.m.
However, with a solder layer thickness of 3 .mu.m or less, the solderability in mounting the semiconductor device onto the substrate will be degraded. This indicates that reduction of the thickness of solder plating is not feasible.
Accordingly, it was difficult to prevent the solder layer deformation by regulating the solder layer thickness.
As described heretofore, in order to prevent the solder layer deformation, reduction of the clamping pressure on the mold as well as reduction of the thickness of the solder plating layer was tried and investigated only to exhibit insufficiency.
In order to eliminate the solder layer deformation, Japanese Patent Application Laid-Open Hei 3 No. 191557 discloses a method in which no solder plating is provided in clamping portion 11.
However, since the positioning deviation of solder plating at present is .+-.0.4 mm, if the solder plating would be omitted in the clamping portion of the mold, semiconductor devices having short outer leads may fail to be solder-plated in their outer lead portion. Therefore, it was found that this method could not be applied to all kinds of semiconductor devices.
Besides, in this method, the lead portion with no solder layer formed is likely to be exposed outside the resin sealing, resulting in reduction of corrosion resistance as well as forming resin burrs at that portion.